In a semiconductor device or an electronic device, adapted to have interfaces with plural sorts of power supply systems, each having different voltages, a tolerant buffer circuit, also termed an overvoltage tolerant buffer circuit or a mixed voltage circuit, is used, in which a terminal (pad) connected to an output of a tristate buffer circuit driven at a relatively low power supply voltage, can be connected to a terminal (pad) of a circuit, driven at a relatively high power supply voltage. For example, if an output of a tristate output buffer of a semiconductor device, driven by for example a 3 V-power supply, is connected to a bus of a system driven by a 5 V-power supply, a p-channel MOS transistor and an n-channel MOS transistor, forming an output stage of the tristate output buffer, are both turned off during an input mode (when an output is being disabled) to set an output in a high impedance state. In this case, a parasitic diode of the pn-junction is formed in a forward direction from a drain region of the p-channel MOS transistor, forming a pull-up driving side of the output stage, to which is applied 5 V, towards an n-well region (3 V power supply potential), such that reverse current flow occurs from an output terminal to the power supply potential within the semiconductor device. For inhibiting the reverse current flow by this parasitic diode, there is known a structure for isolating the well region of the p-channel MOS transistor, forming the pull-up driving side of the output stage, from the power supply potential. See for example the following reference (termed as a patent publication 1).
[Patent Document 1]
Japanese Patent Kokai Publication JP-A-9-238065 (see pages 3 and 4 and FIG. 1)
For understanding of a conventional tolerant buffer circuit, the circuit proposed in the above patent publication 1 is described as an example. FIG. 15 hereof shows the circuit structure described in this patent publication 1, in which the reference numerals are partially changed from those used in the patent publication 1. In FIG. 15, an output stage 1 is composed by a CMOS circuit made up by a p-channel MOS transistor P11 for pull-up driving (charging) connected across a power supply potential Vcc (+3 V) and an output terminal 11 and by an n-channel MOS transistor N11 for pull-down driving (discharging), connected across the output terminal 11 and the ground (GND). The p-channel MOS transistor P11 for pull-up driving has a well region n1 separated from the power supply Vcc (source side).
A pre-stage circuit 2 is made up by CMOS logic gates G1 and G2 and a CMOS inverter Iv2. When an enable signal E is at a high level, the pre-stage circuit is responsive to an input signal A to output a signal for complementary on/off control of the p-channel MOS transistor P11 and the n-channel MOS transistor N11 of the output stage 1. A tristate control circuit 3 is made up by CMOS inverters Iv31 and Iv32, p-channel MOS transistors P12 to P15, and n-channel MOS transistors N12 to N14. With the enable signal E at a low level, the tristate control circuit turns off both the p-channel MOS transistor P11 and the n-channel MOS transistor N1 of the output stage 1. The p-channel MOS transistors P11 to P15 are formed in the common well region n1. Of these, the p-channel MOS transistor P12 is interposed between the well region n1 of the p-channel MOS transistors P11 and the power supply Vcc and forms a well control circuit which, during enable time (signal E =high) or during disable time (signal E =low), connects the well region n1 to the power supply potential Vcc or disconnects the well region n1 from the power supply potential Vcc (source of the p-channel MOS transistor P11). The p-channel MOS transistor P13, having a gate connected to the power supply potential Vcc and having a drain and a source connected to a drain and a gate of the p-channel MOS transistor P11, respectively, forms a voltage by-pass circuit for forming a by-pass across the drain and gate of the p-channel MOS transistor P11 so that, when a high voltage of, for example, +5 V, is applied to the output terminal 11, the drain-to-gate voltage of the p-channel MOS transistor P11 does not exceed a thresholds value.
The p-channel MOS transistor P14 and the n-channel MOS transistor N12 form an input isolating circuit which, during the enable time, connects the gate of the p-channel MOS transistor P11 to the pre-stage circuit 2 (output of a CMOS logic gate GI) and, during the disable time, cuts off the gate of the p-channel MOS transistor P11 from the pre-stage circuit 2. During the disable time, the p-channel MOS transistor P15 and the n-channel MOS transistor N13 forms a MOS switching circuit for connecting the gates of the p-channel MOS transistors P12 and P14, forming the well controlling circuit and the input separation circuit, to the output terminal during the disable time.
If, in the circuit shown in FIG. 15, the enable signal E is set to a high level to set the enable state, the p-channel MOS transistor P11 of the output stage 1 is on/off controlled by the input signal A supplied via logic gate G1 and the MOS transistors N12, P14, while the n-channel MOS transistor N11 of the output stage 1 is on-off controlled complementarily with respect to the p-channel MOS transistor P11, by the input signal A supplied via the logic gate G2 and the inverter Iv2, in order to control the output terminal 11 to high or low responsive to the input signal (data signal) A. The p-channel MOS transistor P11 of the output stage 1 is turned on or off, at this time, as the well region n1 is connected via p-channel MOS transistor P12 to Vcc (+3 V). If the enable signal E is set to a low level (disabled state), the outputs of the logic gates G1 and G2 are set to a high level, without dependency on the state of the input signal A, and hence the p-channel MOS transistor P11 and the n-channel MOS transistor N11 are both set to the off-state, with the output being in a high-impedance state. If, in the disabled state, a voltage higher than the power supply potential Vcc is applied, the reverse current flow by the parasitic diode Ds of the p-channel MOS transistor P11 is inhibited, in such a manner as to inhibit the reverse current flow by the drain voltage of the p-channel MOS transistor P11 exceeding the reverse threshold value across the drain and the gate.